Project
| # | Title | Team Members | TA | Documents | Sponsor |
|---|---|---|---|---|---|
| 76 | FPGA-based stock market data feed handler |
Neel Ghosal Saksham Jairath Sara Sehgal |
Gerasimos Gerogiannis | design_document2.pdf proposal1.pdf |
|
| Problem Electronic trading systems must process extremely high-rate streams of market data with very low and predictable latency. Software-based feed handlers running on general-purpose CPUs often suffer from nondeterministic delays due to instruction overhead, caching, and operating system scheduling, which can lead to delayed reactions or dropped messages under heavy load. Hardware-based solutions are therefore commonly used in industry to achieve deterministic performance. This project addresses the need for a low-latency, reliable market data processing system. Solution We propose an FPGA-based hardware market data feed handler that processes packetized trading updates in real time. The system ingests a continuous byte stream, parses market data messages, maintains per-symbol trading state (top-of-book), and generates low-latency trigger events when predefined conditions are met. By implementing the data path entirely in hardware, the design provides deterministic latency and high throughput, demonstrating the advantages of hardware acceleration for latency-critical trading workloads. Solution Components Subsystem 1: Input Interface and Buffering Receives incoming data via the FPGA’s UART interface and buffers it using a FIFO implemented in block RAM to prevent data loss during bursts. Components: FPGA UART, BRAM FIFO. Subsystem 2: Packet Parser A finite state machine parses incoming bytes into structured market data messages based on a predefined packet format. Components: SystemVerilog FSM. Subsystem 3: Trading State Manager Maintains best bid and best ask prices per symbol and updates state based on incoming messages. Components: BRAM, comparison logic. Subsystem 4: Trigger Engine and Output Evaluates trading conditions and outputs trigger events and system metrics via UART. Components: Arithmetic/comparison logic, UART transmitter. Criterion For Success Correctly parses all valid packets and updates top-of-book state to match a software reference model. Sustains a target message throughput without data loss. Produces deterministic, bounded latency from packet reception to trigger generation. Detects and reports sequence gaps or malformed packets. Meets FPGA resource and timing constraints. |
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