Our group is designing a ~5 Gb/s NRZ-based SerDes receiver in TSMC 65 nm CMOS. The receiver incorporates a Continuous-Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR) loop, and deserializer (DEMUX) to mitigate channel loss and recover data from high-speed differential links. The design targets a bit error rate below 10 , operation from a nominal 1 V supply, and less than 1 mm² silicon area. As an advanced feature, we are exploring both programmable and adaptive equalization techniques to improve performance across dynamic channel conditions.