This chip is a unified data transformation accelerator that runs ChaCha20, SHA-256, CRC-32, HMAC, and custom user algorithms on one shared pool of ARX functional units (ADD, XOR, AND, SHIFT) instead of a dedicated datapath per algorithm. An iterative controller time-multiplexes those units, routing operands cycle by cycle via self-describing instructions, so new and user-uploaded algorithms are processed as well. A 512-bit register file supports 32-bit and 128-bit SIMD modes, with a mixed-signal TRNG for on-chip entropy.