Illinium is an RTL simulation/emulation accelerator composed of an array of processing elements, each computing a logic function per clock cycle. Instead of mapping the design onto a fixed fabric like an FPGA, Illinium stores the emulated circuit’s combinational and sequential state in onchip SRAM and steps through one emulated cycle over multiple system clock cycles. This time multiplexed operation gives Illinium much higher logic density over an FPGA of the same die size. Moreover, this architecture allow us to replace time consuming place-and-route (pnr) setup with a much simpler netlist generation/compilation flow, where the netlist is compiled into a sequence of instructions describing logic functions.