ECE 427: Advanced VLSI System Design
Lecture Time: TR 11:00-11:50 ECEB 3017
Instructor: Dong Kai Wang
Jerry Wang (tw12@illinois.edu)
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Fall 2026 Projects
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Illinium: Accelerator for RTL Emulation
Illinium is an RTL simulation/emulation accelerator composed of an array of processing elements, each computing a logic function per clock cycle.
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Gigatoe: TCP Offload Engine
This project implements a TCP Offload Engine (TOE) designed for low-latency embedded systems operating over 1 Gb/s Ethernet.
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FORTE: Fault-tOlerant RISC-V with Trusted Enclaves
FORTE (Fault-tOlerant RISC-V with Trusted Enclaves) is an open-source Linux-capable RISC-V processor combining physical memory protection (PMP), a hardware root of trust (RoT), and hardware-level fault tolerance mechanisms.
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SWISS: A CGRA with RISC-V Timesharing
SWISS is an AI inference accelerator built around an 8×8 systolic-array Matrix Multiply Unit (MXU) that is specifically optimized for NVIDIA-style 2:4 structured sparsity.
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High-Speed NRZ SerDes Receiver in 65-nm CMOS
High-Speed NRZ SerDes Receiver in 65-nm CMOS
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ATLAS - ARX Transformation Logic Acceleration System
A unified data transformation accelerator that runs ChaCha20, SHA-256, CRC-32, HMAC, and custom user algorithms.