Course Information
Course description
In this course, we will discuss advanced computer architecture techniques. The course will cover a variety of latest research topics centered around the computer architecture, including instruction set architecture, multi-core processors, parallel programming models and architecture, heterogeneous computing systems, processor security, hardware accelerators and virtualization, cache architecture, memory subsystem, memory consistency and persistency models, near-data processing, disaggregated computing architecture, and unconventional computer architecture like brain-computer interface. Through this course, students will learn not only the fundamental concepts of computer architecture via the lecture materials, but also the hands-on experience of designing and evaluating architecture techniques via MPs and a course project.
Who is this course for?
ECE511 is primarily intended for motivated seniors and graduate students who want to learn the latest research advances in computer architecture.
Prerequisite
ECE411 Computer Organization and Design (or similar basic computer architecture course)
Quick Links
Communication and Q&A for this course will be on Piazza. Gradescope and Canvas will be used to handle assigment submissions and grading. If you’ve signed up for the class, you should be auto-enrolled in these platforms. Please ensure you can access them at the links below.
Class Times
Instructor: Professor Jian Huang
Lecture: 9:00AM - 10:20AM, Tuesdays & Thursdays, ECEB 3017
TAs
Noelle Crawford (noellec3@illinois.edu)
Michael Wang (mjwang6@illinois.edu)
Office hours
- Prof. Huang (jianh@illinois.edu)
When/Where: After class, 10:30AM-11:00AM Tuesdays & Thursdays
- Noelle Crawford (noellec3@illinois.edu)
3:00PM-4:00PM Wednesdays in CSL 239
- Michael Wang (mjwang6@illinois.edu)
3:30PM-4:30PM Fridays in CSL 239
Grading policy
- In-class Pop-quiz (35%)
Questions & answers for basic concepts
5 quizzes, each quiz will take about 20 minutes
- Programming Assignments (30%)
MP0 (0%): Student Information Sheet
MP1 (12%): Gem5 simulator system
MP2 (9%): GPU architecture simulator
MP3 (9%): A study of DRAM architecture
- Course Project or MP4 (TBD) (35%)
Milestone-1 (4%): related work summary. Each team should submit an investigation of related work.
Milestone-2 (8%): submit a project proposal and discuss with the instructor. Proposal would be revised after discussion.
Milestone-3 (4%): in-class presentation of the proposed project.
Milestone-4 (4%): middle-term checkpoint (a short technical report with preliminary results) and progress discussion with the instructor.
Milestone-5 (5%): in-class demo and presentation.
Milestone-6 (10%): final report and source code.