CS 433 / CSE 422

Paper Reviews

• Guidelines for Writing a Paper Review

Set 1: Going Further in Program Execution

• Fisher, "Very Long Instruction Word Architectures and the ELI-512", ISCA, 1983
• Jiménez and Lin, "Dynamic Branch Prediction with Perceptrons", HPCA, 2001
• Srinath et al., "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers", HPCA, 2007

Set 2: Advanced Speculation Research

• Palacharla et al., "Complexity-Effective Superscalar Processors", ISCA, 1997
• Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors", HPCA, 2003
• Kocher et al., "Spectre Attacks: Exploiting Speculative Execution", S&P, 2019

Set 3: Expanding Memory Subsystem Functionality

• Qureshi and Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", MICRO, 2006
• Rotenberg et al., "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching", MICRO, 1996
• Seshadri et al., "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology", MICRO, 2017
• Pham et al., "CoLT: Coalesced Large-Reach TLBs", MICRO, 2012

Set 4: Exploiting TLP and DLP

• Tullsen et al., "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", ISCA, 1996
• Sankaralingam et al., "Exploiting ILP, TLP, and DLP With the Polymorphous TRIPS Architecture", ISCA, 2003
• Kumar et al., "Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance",, ISCA, 2004
• Hammond et al., "Transactional Memory Coherence and Consistency", ISCA, 2004