Readings
| Lecture # | Date | Readings |
|---|---|---|
| 1 | 01/21/2025 T | Introduction: Technology and Performance [Review] Coming Challenges in Microarchitecture and Architecture https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=915377 |
| 2 | 01/23/2025 R | Gem5 Tutorial: See Resources [Read]: The gem5 Simulator: Version 20.0+ https://arxiv.org/abs/2007.03152 [Reference] Learning gem5: https://www.gem5.org/documentation/learning_gem5/introduction/ [Reference] Morgan Claypool Lecture on Simulation: https://link.springer.com/content/pdf/10.1007/978-3-031-01727-8.pdf |
| 3 | 01/28/2025 T | Instruction Fetch [Read] The Microarchitecture of Superscalar Processors https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=476078 [Review] Optimization of instruction fetch mechanisms for high issue rates https://ieeexplore.ieee.org/document/524573 |
| 4 | 01/30/2025 R | Speculative Execution / OoO (I) [Review] The MIPS R10000 Superscalar Microprocessor https://ieeexplore.ieee.org/document/491460 [Reference] Processor Microarchitecture An Implementation Perspective. Chapters 5 and 6 |
| 5 | 02/04/2025 T | Speculative Execution / OO (II) [Read] Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers https://ieeexplore.ieee.org/document/48865 [Review] Implementing Precise Interrupts in Pipelined Processors https://ieeexplore.ieee.org/iel1/12/257/00004607.pdf |
| 6 | 02/06/2025 R | Memory Dataflow [Read] Scalable Hardware Memory Disambiguation for High ILP Processors https://www.microarch.org/micro36/html/pdf/sethumadhavan-ScalableHardware.pdf [Review] Memory Dependence Prediction using Store Sets https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=694770 |
| 7 | 02/11/2025 T | Hardware Tutorial [Read] An Efficient Algorithm for Exploiting Multiple Arithmetic Units https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5392028 |
| 8 | 02/13/2025 R | Execution and Commit [Review] Complexity Effective Superscalar Processors (ISCA’97) https://dl.acm.org/doi/pdf/10.1145/264107.264201 |
| 9 | 02/18/2025 T | Caches and Memory (I) [Review] Sandbox Prefetching: Safe Run-Time Evaluation of Aggressive Prefetchers https://www.cs.utah.edu/~rajeev/pubs/hpca14p.pdf [Reference] A Primer on Hardware Prefetching https://link.springer.com/content/pdf/10.1007/978-3-031-01743-8.pdf |
| 10 | 02/20/2025 R | Caches and Memory (II) [Review] Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems https://ieeexplore.ieee.org/document/8686544 [Read] High-performance DRAMs in workstation environments https://ieeexplore.ieee.org/document/966491 [Reference] The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It https://link.springer.com/content/pdf/10.1007/978-3-031-01724-7.pdf |
| 11 | 02/25/2025 T | Multi-core Processor / Multithreading [Read] The Case for a Single-Chip Multiprocessor (ASPLOS’96) https://dl.acm.org/doi/10.1145/248209.237140 [Review] Chip Multithreading: Opportunities and Challenges (HPCA’05) https://ieeexplore.ieee.org/document/1385946 |
| 12 | 02/27/2025 R | Midterm Exam |
| 13 | 03/04/2025 T | Coherence, Consistency, and Synchronization (I) [Review] Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors (ISCA’90) https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/papers/ieeemicro96-adve-consistency.pdf |
| 14 | 03/06/2025 R | Coherence, Consistency, and Synchronization (II) [Read] A Primer on Memory Consistency and Cache Coherence https://link.springer.com/content/pdf/10.1007/978-3-031-01733-9.pdf |
| 15 | 03/11/2025 T | Transactional Memory [Review] Transactional Memory: Architectural Support for Lock-Free Data Structures https://cs.brown.edu/~mph/HerlihyM93/herlihy93transactional.pdf [Read] Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution https://pages.cs.wisc.edu/~rajwar/papers/micro01.pdf |
| 16 | 03/13/2025 R | Interconnection networks [Read] A Survey of Wormhole Routing Techniques in Direct Networks https://ieeexplore.ieee.org/document/191995 [Review] In-network cache coherence https://dl.acm.org/doi/10.1109/MICRO.2006.27 |
| 03/18/2025 T | Spring Break | |
| 03/20/2025 R | Spring Break | |
| 17 | 03/25/2025 T | Multiprocessors, Supercomputers, and Datacenter architecture [Read] The Datacenter as a Computer (Chapter 3) (Synthesis Lecture on Computer Architecture) https://link.springer.com/content/pdf/10.1007/978-3-031-01761-2.pdf |
| 18 | 03/27/2025 R | Power efficient architectures [Review] Power: A First Class Design Constraint for Future Architecture and Automation https://dl.acm.org/doi/10.5555/645446.653205 |
| 19 | 04/01/2025 T | Chiplets and Packaging [Read] Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor families https://dl.acm.org/doi/10.1109/isca52012.2021.00014 [Review] Architecting Waferscale Processors - A GPU Case Study (HPCA’19) https://passat.crhc.illinois.edu/hpca19_cam.pdf |
| 20 | 04/03/2025 R | Processor Reliability and Security [Read] Understanding Silent Data Corruptions in a Large Production CPU Population https://dl.acm.org/doi/pdf/10.1145/3600006.3613149 [Read] Meltdown: Reading Kernel Memory from User Space https://www.usenix.org/system/files/conference/usenixsecurity18/sec18-lipp.pdf [Review] Spectre Attacks: Exploiting Speculative Execution https://www.spectreattack.com/spectre.pdf |
| 21 | 04/08/2025 T | Final Exam |
| 22 | 04/10/2025 R | GPUs and application-specific hardware [Read] In-Datacenter Performance Analysis of a Tensor Processing Unit (ISCA’17) https://dl.acm.org/doi/10.1145/3079856.3080246 [Review] Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin https://vlsiarch.eecs.harvard.edu/publications/co-designing-accelerators-and-soc-interfaces-using-gem5-aladdin |
| 23 | 04/15/2025 T | Processing in Memory |
| 24 | 04/17/2025 R | Hardware Virtualization |
| 25 | 04/22/2025 T | Rethinking Virtual Memory |
| 26 | 04/24/2025 R | TBD |
| 27 | 04/29/2025 T | Project Presentations |
| 28 | 05/01/2025 R | Project Presentations |
| 29 | 05/06/2025 T | TBD |