ECE 483: Analog IC Design (Spring-2025)

Project Description:

LDO Project Handout

LDO Tutorial Video

Cadence Files:

Project Files

• “ldo_model” is a simulation model to simulate and determine the required specs of your amplifier.

• “ldo” is a schematic and symbol to allow for autograder testing. Your design should reside completely in this symbol.
  Note: do not place symbols inside of this symbol.

• “tb_project” is a testbench to test your “ldo” schematic.

Matlab Files:

Look up table

Drawing Setup

Visio Files

Drawing symbols (place in Documents/My Shapes, use line thickness 1.5)

Project Upload:

Autograder Zip: zip Note: this will be released at a later date.

Upload the netlist to Box: Submit
The uploaded netlist must be named as “netid1_netid2_netlist”.
If you need to submit a new version just re-upload with the same file name and we will use the latest uploaded version.