Lectures

Date	Slides	Accompanying Material	Recordings
8/22/2023	Lecture 1 - Introduction and Overview		Lecture 1
8/24/2023	Lecture 2 - SoC Design Methodology and IP	Chapter 38: Design Automation for Microelectronics, Handbook of Automation Industrial IP Integration Flows based on IP-XACT Standards	Lecture 2
8/29/2023	Lecture 3 - Lab and MP Overview	Verilog Overview The Verilog Hardware Description Language 5th Edition	Lecture 3
8/31/2023	Lecture 4 - Embedded Systems	Embedded Software Improving Embedded Software Design and Integration in SoCs	Lecture 4
9/5/2023	Lecture 5 - Hardware	System-Level Design Solutions: Enabling the IoT Explosion	Lecture 5
9/7/2023	Lecture 6 - Reconfigurable Computing MP 2 Lab Session Slides (9/11/2023)	Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures A Novel SoC Architecture on FPGA for Ultra Fast Face Detection	Lecture 6 MP2 Lab Recording
9/12/2023	Lecture 7 - System Modeling		Lecture 7
9/14/2023	Lecture 8 - Accelerator Design	Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration	Lecture 8
9/19/2023	Lecture 9 - HLS	Designing High Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis	Lecture 9
9/21/2023	Lecture 10 - HLS Coding Style		Lecture 10
9/26/2023	Lecture 11 - Synthesizability and Layout-driven HLS		Lecture 11
9/28/2023	Lecture 12 - Scheduling	Force-Directed Scheduling for the Behavioral Synthesis of ASIC's Material on ILP from "Synthesis and optimization for digital circuits"	Lecture 12
10/03/2023	Lecture 13 - Binding	LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization	Lecture 13
10/05/2023	Lecture 14 - MLIR, ScaleHLS, and HIDA MP 4 Lab Session Slides (10/09/2023)	MLIR: Scaling Compiler Infrastructure for Domain Specific Computation [HPCA'22] ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation [DAC'22] ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations [ASPLOS'24] HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis	Lecture 14
10/10/2023	Lecture 15 - FCUDA: The CUDA to FPGA Compiler	Multilevel Granularity Parallelism Synthesis on FPGAs FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs	Lecture 15
10/12/2023	Lecture 16 - Final Project		Lecture 16
10/17 and 10/19 2023	Lecture 17 and 18 - HW/SW Co-design	Codex-dp: Co-design of Communicating Systems Using Dynamic Programming Parallel Code-Specific CPU Simulation with Dynamic Phase Convergence Modeling for HW/SW Co-Design A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration Accurate High-Level Modeling and Automated Hardware/Software Co-Design for Effective SoC Design Space Exploration	Lecture 17 Lecture 18
10/24/2023	Lecture 19 - Fundamentals of DNNs		Lecture 19
10/26/2023 and 11/2/2023	Lecture 20 and 21 - DNN Inference Acceleration	High-Performance Video Content Recognition with Long-term REcurrent Convolutional Network for FPGA DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks	Lecture 20 Lecture 21
11/7/2023	Lecture 22 - ML Algorithm and Hardware Codesign	EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions SKYNET: A HARDWARE-EFFICIENT METHOD FOR OBJECT DETECTION AND TRACKING ON EMBEDDED SYSTEMS	Lecture 22
11/9/2023	Lecture 23 - TEE	AccGuard AccShield	Lecture 23
11/14/2023	Lecture 24 - Invited Lecture by Martin Langhammer: The FPGA as SoC		Lecture 24
11/16/2023	Lecture 25 - Invited Lecture by Stephen Neuendorffer: Open Source MLIR Compilers for Versal Ryzen AI SOCs		Lecture 25
11/28/2023	Student Presentations Day 1		Lecture 26
11/30/2023	Student Presentations Day 2		Lecture 27

ECE 527

SoC Design

Fall 2023

Lectures

Date

Slides

Accompanying Material

Recordings