ECE 498HK: Advanced VLSI System Design 

Current Students: Join Class Site on Canvas

Current Projects: Fall 2024 Project Page

Instructor: Dong Kai Wang

Email: dwang47@illinois.edu (Include [ECE498HK] in subject line)

Grad TA: Stanley Wu

Email: zaizhou3@illinois.edu (Include [ECE498HK] in subject line)

Quick Links

VM Access: EDA VM Infrastructure and Access

Reference Texts: Reference Texts for VLSI Design

Detailed Syllabus: ECE498HK Syllabus.pdf

Groups Signup: Google Sheets

Course Objectives

Students will work in teams of 5-6 to design and fabricate their own digital, analog, or mixed-signal chip using modern electronic design automation (EDA) tools and industry best practices. In this project-based course, each team will propose a design in the form of specifications, write a Verilog (or equivalent) and a synthesizable C++ (or equivalent) model for the chip or its components, design schematics, create a testing/debug strategy, and perform layout, integration, and verification of the chip before taping it out. The design files for fully functional designs will be sent for fabrication at the end of the semester. Students can test their devices as an individual study course when the chips come back from the foundry. We will be requiring (at least) one of the team members to commit to enrolling in an independent study to test the chips. Roughly nine to eleven hours of lab work is expected per week. Overall, the course will require a time commitment of 13-15 hours per week. Prerequisites: Some prior experience with hardware design and layout will be necessary.

Course Schedule

Major Assignments

• Project Proposal – Proposal document and presentation describing the project’s goals, high-level design, task division, and timeline. Due on the second week of class.
• Midterm Report – Progress report documenting completed designs, verification coverage, schematics and layouts done halfway through the semester. Digital projects are expected to complete RTL design by this deadline.
• Trial GDS – Trial GDSII file handed to MPW partner for initial design rule checks, students will have a chance to fix violations after getting feedback from foundry.
• Final GDS – Final GDSII file handed to MPW partner, and subsequently to foundry for tapeout. Accompanying specifications and DRC waivers must also be completed.
• Final Report – Final project report in IEEE conference paper style documenting the entire design, specifications, verification and test strategies, and challenges faced throughout the entire project.

Weekly Progress Meetings

In addition to the midterm and final progress reports, there will be two minor group progress reviews in class. Furthermore, each group is required to meet with course staff every week to discuss their progress. We recommend that all group members attend but exceptions can be made if scheduling is difficult.

Acknowledgments

This offering of ECE498HK is supported by Intel VLSI Curriculum Funding. We thank our industry sponsors for making this class possible.