ECE 498HK: Advanced VLSI System Design (Fall 2023)

 

IMPORTANT: Class Website Moved to Canvas

 

Instructor: Dong Kai Wang

Email: dwang47@illinois.edu (Include [ECE498HK] in subject line)

OH Signup / ScheduleGoogle SheetsLinks to an external site.

Monday 10:30-11:30AM ECEB 2036

Wednesday 10:30-11:30AM ECEB 4036

Thursday 12:00-1:00PM ECEB 2066

TAs: Stanley Wu (Digital), Mahmoud Khalil (Analog)

Stanley: zaizhou3@illinois.edu (Include [ECE498HK] in subject line), Office hours: Monday 2:00-3:00PM ECEB 2036

Mahmoud: mkhalil4@illinois.edu (Include [ECE498HK] in subject line), Office hours: Contact & Arrange

 

Quick Links

VM Access: EDA VM Infrastructure and Access

Reference Texts: Reference Texts for VLSI Design

Groups SignupGoogle SheetsLinks to an external site.

Campuswire: CampuswireLinks to an external site.

Zoom for (Remote) Office Hours / Lectures:
https://illinois.zoom.us/j/9232349196?pwd=ZVE0K0tjQ1IzZE5HZkVxN3B4aHRIUT09Links to an external site.
Zoom Meeting ID: 923 234 9196 Password: DKW

 

Course Objectives

Students will work in teams of 5-6 to design and fabricate their own digital, analog, or mixed-signal chip using modern electronic design automation (EDA) tools and industry best practices. In this project-based course, each team will propose a design in the form of specifications, write a Verilog (or equivalent) and a synthesizable C++ (or equivalent) model for the chip or its components, design schematics, create a testing/debug strategy, and perform layout, integration, and verification of the chip before taping it out. The design files for fully functional designs will be sent for fabrication at the end of the semester. Students can test their devices as an individual study course when the chips come back from the foundry. We will be requiring (at least) one of the team members to commit to enrolling in an independent study to test the chips. Roughly nine to eleven hours of lab work is expected per week. Overall, the course will require a time commitment of 13-15 hours per week. Prerequisites: Some prior experience with hardware design and layout will be necessary.

 

Course Schedule

(Green - Online Lectures, Purple - Special Topics) *Subject to Change

Date

Lecture

Expected Project Timeline

08/24/2023

Course Introduction

(ECE498HK Lecture 1.pptx Download ECE498HK Lecture 1.pptx)

(ECE498HK Lecture 1.zip Download ECE498HK Lecture 1.zip)

Environment Setup

08/31/2023

Project Proposal Presentations

(ECE498HK Lecture 2.zip Download ECE498HK Lecture 2.zip)

Hardware Design Phase

09/07/2023

EDA Workflow Tutorial

(ECE498HK Lecture 3.zip Download ECE498HK Lecture 3.zip)

 

09/14/2023

Design for Synthesis & Verification

(ECE498HK Lecture 4.pptx Download ECE498HK Lecture 4.pptx)

 

09/21/2023

Hardware Synthesis with DC

(ECE498HK Lecture 5.pptx Download ECE498HK Lecture 5.pptx)

(ECE498HK Lecture 5.zip Download ECE498HK Lecture 5.zip)

Group Progress Review

09/26/2023

Design Compiler Tutorial (ONL)

(Lecture EX - Synopsys DC.pptx Download Lecture EX - Synopsys DC.pptx)

(Lecture EX - Synopsys DC.zip Download Lecture EX - Synopsys DC.zip)

 

09/28/2023

Introduction to Verification and Test

(ECE498HK Lecture 6.pptx Download ECE498HK Lecture 6.pptx)

(ECE498HK Lecture 6.zip Download ECE498HK Lecture 6.zip)

 

09/30/2023

SV Verification (ONL)

(Lecture EX - RTL Verification.pptx Download Lecture EX - RTL Verification.pptx)

(Re-recording Pending)

 

10/03/2023

DFT Compiler Basics (ONL)

(Lecture EX - DFT Compiler.pptx Download Lecture EX - DFT Compiler.pptx)

(Re-recording Pending)

 

10/05/2023

DFT / RTL Verification Cont.

(ECE498HK Lecture 7.pptx Download ECE498HK Lecture 7.pptx)

(ECE498HK Lecture 7.zip Download ECE498HK Lecture 7.zip)

 

10/05/2023

Multiple Clock Domains (ONL)

(Lecture EX - Clock Domains.pptx Download Lecture EX - Clock Domains.pptx)

(Lecture EX - Clock Domains.zip Download Lecture EX - Clock Domains.zip)

 

10/12/2023

Synthesis Review

Introduction to Physical Design

(ECE498HK Lecture 8.pptx Download ECE498HK Lecture 8.pptx)

RTL Freeze

10/19/2023

Mid-Term Report

Physical Implementation

Innovus / Virtuoso Tutorial

Mid-Term Progress Review

Physical Design Phase

10/26/2023

Placement and Routing

Power Optimization

 

11/02/2023

Guest Lecture: ESD / EMI

*Tentative

 

11/09/2023

2.5 & 3D Die Stacking

Advanced Packaging: Chiplets, EMIB

 Group Progress Review

11/16/2023

AI/ML for Chip Design

 

11/23/2023

Fall Break

 

11/30/2023

Validation & Signoff (I)

Group Progress Review

12/07/2023

Validation & Signoff (II)

 

12/14/2023

Project Presentation Week

Final Deadline

 

Grading Policy

Percentage

Assignment

Description

10%

Attendance / Progress Reviews

Attend lectures and progress meetings.

5%

Project Proposal

Proposal document and presentation (week 1).

10%

Mid-Term Report

Written mid-semester progress report (week 8).

10%

Final Presentation

Oral final presentation (week 16).

15%

Final Report

Written final report (week 16).

50%

Project Completion

Final design and physical implementation (week 16).