Deming Chen (dchen AT illinois.edu)
Office hours: Tuesday 2:00 - 3:00 PM Central Time, online. Using office hours Zoom link.
-Eddie Richter (edwardr2 AT illinois.edu)
Office hours: Monday 12:00 - 1:00 PM, Wednesday 12:00 - 1:00 PM Central Time. Using office hours Zoom link.
-Paul Jeong (hyunmin2 AT illinois.edu)
Office hours: Wednesday 1:00 - 2:00 PM, Thursday 3:00 - 4:00 PM Central Time. Using office hours Zoom link.
Online Zoom Meeting
Time: Tuesday/Thursday 11:00 - 12:20 PM Central Time
Zoom Meeting ID: 837 8122 7564
Online Zoom Meeting / 4022 ECE Building (only for tasks where in-person contact is necessary)
We will dedicate Wednesday's office hours to lab sessions.
Time: Wednesday 12:00 - 2:00 PM Central Time
Zoom Meeting ID: 819 7255 0854
ECE 425 (or equivalent), ECE 391 (or equivalent)
System-on-a-chip (SOC) is an idea of integrating all components of a computer system into a single chip. SOC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. Gartner regards them as the most important type of semiconductor device since the development of the microprocessor. An important enabler for the design of SOCs is the availability of semiconductor intellectual property (IP), which allows a SOC designer to include predefined circuitries, cutting development cycle while increasing product functionality, performance and quality. The implementation of these systems of both hardware and software components and the interaction between hardware and software is an essential part of the design. This course will cover SOC topics on design process, modeling and analysis, design methodology and platform, hardware/software co-design, behavioral synthesis, embedded software, verification, and design space exploration. With a focus on learning of the current SOC design and research topics, students are given opportunities to carry out class projects based on their own interest. Class projects can include software/hardware partitioning, hardware implementation of video compression algorithms, and synthesis for application specific instruction set processors (ASIP). Platform FPGA boards and digital cameras are provided to students to prototype, test, and evaluate their SOC designs.
Machine problem 1: 5% (70% actual work + 30% report)
Machine problem 2: 8% (70% actual work + 30% report)
Machine problem 3: 5% (70% actual work + 30% report)
Machine problem 4: 10% (70% actual work + 30% report)
Class participation: 2%
Research Project 40%: (70% actual work + 20% report + 10% presentation)
15% off/day, cannot be more than 3 days late.