The main purpose of this assignment is to give you experience designing and implementing high bandwidth fetch units.
The simulator currently implements a small BTB in the Ifetch stage. Implement a gcskew style branch predictor in the ifetch stage to achieve better branch prediction. You get to choose the predictor parameters. Also note that the simulator already has a return address stack.
Turn in a short (2-3 pages for assignment 2) report on what you implemented and what you learned. You should address questions like the following: What assumptions did you make? What did you try that didn't work? Which of the changes you made were most and least effective? For those features that weren't very effective, why do you think they didn't work very well? In the simulator there is no easy way to estimate the effect of a particular circuit on cycle time, did you choose reasonable structures?