University of Illinois at Urbana-Champaign

Department of Electrical and Computer Engineering

ECE 511: Computer Architecture

Fall 2006

Homework 3

Purpose

The main purpose of this assignment is to help you understand how superscalar renamers work, and how they help performance.

Assignment

The simulator's rename stage currently doesn't do anything. That is to say, the rename stage just assigns each architectural register to the physical register with the same number. In this assignment you are to implement a renamer that actually does renaming. The simulator has all the hooks you need to implement a MIPS R10000 style renamer (as described in Yeager's paper). Note that it is almost certainly easiest to put a single Register Alias Table, Retirement Register Alias Table and Free List all in the rename_stage.

Some notes

The only file you should need to modify is rename_stage.h. The default flags to the simulator are currently set up with 33 physical registers (although only 32 of them are in use given the current renamer). Once you have renaming working there are several simulator flags that you may find interesting to play with:

• -phys_regs lets you set the size of the physical register file (default is 33 physical registers).
• The -ooo_scheduler flag tells the scheduler to issue instructions speculatively past possibly mispredicted branches, and out-of-order (the default is to issue instructions in order).
• The -sched_issue_buffer_size flag lets you set the scoreboard size (default is 64).
• The -rob_size flag lets you change the size of the reorder buffer (default is 64 instructions).
• The -superpipeline flag lets you set the pipeline depth of the execution unit. The default is 4 (i.e. an integer add instruction takes 4 cycles, and 4 integer add instructions can be executing concurrently).

There are also a number of notes about things to watch out for in the rename_stage.h source file itself. In particular, there is a discussion about jump-and-link instructions, which need to be handled a little bit carefully.

What to turn in

You may work alone or in groups of 2. Each group should turn in a short (2-3 pages for assignment 3) report on what you implemented and what you learned. You should address questions like the following: How small can the physical register file be before you start running out of free registers and need to stall fetch? How did changing the reorder buffer and/or scoreboard size and the number of physical registers affect performance? How much did it help to speculate past predicted branches?

The Simulator

The simulator is works on Linux machines and on Cygwin. It has been tested on EWS Linux Lab machines in Engineering Hall, and on a machine running RedHat Linux 9.0

Step 1

Download the tarball for the simulator: ece511-sim.tar.gz

Step 2

Unzip and untar the simulator by running the command:

• tar -zxvf ece511-sim.tar.gz

This will create a source directory named "ece511". The source directory has the following structure:

+--- ece511 +---- apps +-------- lzw    (spec benchmark)
            |          +-------- gcc    (spec benchmark)
            |          +-------- bzip2  (spec benchmark)
            |          +-------- parser (spec benchmark)
            |          +-------- mcf    (spec benchmark)
            | 
            +---- (the simulator code)

Step 3

Run make in the ece511/ directory:

• make

This compiles the simulator

Step 4

Compile and run a program on the simulator:

• cd ece511/apps/lzw
• make small.out

(lzw is a version of the unix compress program. It creates a buffer of random text, then compresses and decompresses the text). While it is running it prints out the random text and then some statistics:

../../pipelined-model mipsver 800
loading segment: start 0x00000080, size 0x003ac5e0, permissions rwx
Entry point 0x00001274
.text is from 0x00000080 to 0x00009a30
SPEC 129.compress harness
Initial File Size:800   Start character:q

The starting size is: 802

The compressed size is: 608

The compressed/uncompressed size is: 802
Files both have length 802
Characters match.
processor halted

Number of cycles run: 2352059
Number of instructions: 952102
utilization: 0.404795

doubled clock gives equivalent speed to single-pump IPC of 0.809590

cache hits: 193835, cache misses: 24379
branches: 103858, mispredicted 7745
mispredictiction rate: 0.074573

Step 5

Make changes to the simulator. The simulator code is in the directory ece511/. For the third assignment you need only modify the file rename_stage.h. To rebuild the simulator go to the directory ece511/ and type make. You may also try some of the other benchmarks instead of lzw.