The main purpose of this assignment is to give you experience designing and implementing high bandwidth fetch units.
The simulator currently implements a small BTB in the ifetch stage. This BTB achieves a branch prediction rate of around 80%. Implement a gshare style branch predictor in the ifetch stage (in file ifetch.h) to achieve better branch prediction. You get to choose the predictor parameters. Also note that the simulator already has a return address stack.
You may work alone or in groups of 2. In previous years I have observed that people working in groups of 2 got the most out of the assignments (and the course). Each group should turn in a short (2-3 pages for assignment 2) report on what you implemented and what you learned. You should address questions like the following: What assumptions did you make? What did you try that didn't work? Which of the changes you made were most and least effective? For those features that weren't very effective, why do you think they didn't work very well? In our simulator there is no easy way to estimate the effect of a particular circuit on cycle time, did you choose reasonable structures?
The simulator is works on Linux machines and on Cygwin. It has been tested on EWS Linux Lab machines in Engineering Hall, and on a machine running RedHat Linux 9.0
Download the tarball for the simulator: ece511-sim.tar.gz (same file as last time, you don't need to download it again if you already have it).
Unzip and untar the simulator by running the command:
This will create a source directory named "ece511". The source directory has the following structure:
+--- ece511 +---- apps +-------- lzw (spec benchmark)
| +-------- gcc (spec benchmark)
| +-------- bzip2 (spec benchmark)
| +-------- parser (spec benchmark)
| +-------- mcf (spec benchmark)
|
+---- (the simulator code)
Run make in the ece511/ directory:
This compiles the simulator
Compile and run a program on the simulator:
(lzw is a version of the unix compress program. It creates a buffer of random text, then compresses and decompresses the text). While it is running it prints out the random text and then some statistics:
../../pipelined-model mipsver 800 loading segment: start 0x00000080, size 0x003ac5e0, permissions rwx Entry point 0x00001274 .text is from 0x00000080 to 0x00009a30 SPEC 129.compress harness Initial File Size:800 Start character:q The starting size is: 802 The compressed size is: 608 The compressed/uncompressed size is: 802 Files both have length 802 Characters match. processor halted Number of cycles run: 2352059 Number of instructions: 952102 utilization: 0.404795 doubled clock gives equivalent speed to single-pump IPC of 0.809590 cache hits: 193835, cache misses: 24379 branches: 103858, mispredicted 7745 mispredictiction rate: 0.074573
Make changes to the simulator. The simulator code is in the directory ece511/. For the second assignment you will mainly be modifying the file ifetch.h. To rebuild the simulator go to the directory ece511/ and type make.