The tutorial is here: circuit_tutorial.pdf
The reference manual is here: ece511-isa.pdf
Homework2 onwards, when you do make in the sim directory,
among other things, you'll get an executable called objdump. You can use it to
disassemble binaries that you run on the simulator. For example, to look at the assembly
code for lzw, in the sim directory, type
./objdump ../apps/lzw/mipsver > lzw.s
You can then open lzw.s in a text editor.
When you do make small.out in the apps/lzw directory, the following command is run:
../../sim/pipelined-model mipsver 800
The simulator executable is called pipelined-model, and the lzw binary is called mipsver.
Also, if you look in the 'apps' directory, you'll find a few other spec benchmarks (gcc, bzip2, parser, mcf). The binaries for all benchmarks are
called mipsver. Most spec benchmarks need some command line parameters. Gcc, for example, needs a .c file that it
can compile. The makefile for each benchmark gives it the necessary command-line parameters. When you do make in the gcc directory,
for example, the following command is executed:
../../sim/pipelined-model mipsver data/tiny.in -o tiny.s
gcc: type make tiny.out for a short input
type make small.out for a longer input
bzip2: type make small.out for a short input
type make med.out for a longer input
mcf: type make test.out for a short input
type make small.out for a longer input
Both inputs take some time to run
parser: type make super-small.out for a super-short input
type make test.out for a short input
type make smred.out for a short input
All three take some time to run
../../sim/pipelined-model -debug 0xffff mipsver 800the simulator will print some useful information, which you can use to debug.
-debug Use bit mask, mask[31:0], to turn on debugging output:
A default setting of all zeroes gives no ouput
0. Debug info for instruction fetch stage
1. Debug info for decoder stage
2. Debug info for register renaming state
3. Debug info for scoreboard stage
4. Debug info for the rob stage
5. Debug info for register file stage
6. Debug info for execution stage
7. Show current and retirement RATs
8. Show register renamer free list
9. Show scoreboard fifo destination regs
10. Show ROB destination regs
11. Show store addresses and data
12. Show load addresses and data
13. Print architectural dest reg and data for each retiring instruction
14. Debug info for caches
-debug_delay Wait until this cycle n before displaying debug info
Example of using debug mask with full debug info:
Debug mask = 111111111111111 in binary or 0x7fff in hex
pipelined-model -debug 0x7fff mipsver 5
Example of just turning on debug info for instruction fetch:
pipelined-model -debug 1 mipsver 5
ddd pipelined-model &