The main purpose of this assignment is to help you understand how superscalar renamers work, and how they help performance.
The simulator's rename stage currently doesn't do anything. That is to say, the rename stage just assigns each architectural register to the physical register with the same number. In this assignment you are to implement a renamer that actually does renaming. The simulator has all the hooks you need to implement a MIPS R10000 style renamer (as described in Yeager's paper). Note that it is almost certainly easiest to put the Register Alias Table, Retirement Register Alias Table and Free List all in the rename_stage.
The only file you should need to modify is rename_stage.h. The default flags to the simulator are currently set up with 64 physical registers (although only 32 of them are in use given the current renamer). Once you have renaming working there are several simulator flags that you may find interesting to play with: -phys_regs lets you set the size of the physical register file (default is 64 physical registers, twice as many as there are architectural registers). The -speculate flag tells the scoreboard to speculatively issue instructions past predicted branches (the default is to disallow instructions after a not-yet-issued branch to issue). The -sbrd_fifo flag lets you set the scoreboard size (default is 64). The -rob_size flag lets you change the size of the reorder buffer (default is 64 instructions). The -superpipeline flag lets you set the pipeline depth of the execution unit. The default is 4 (i.e. an integer add instruction takes 4 cycles, and 4 integer add instructions can be executing concurrently).
There are also a number of notes about things to watch out for in the rename_stage.h source file itself. In particular, there is a discussion about jump-and-link instructions, which need to be handled a little bit carefully.
You may work alone or in groups of 2, 3 or 4. Each group should turn in a short (2-3 pages for assignment 3) report on what you implemented and what you learned. You should address questions like the following: How small can the physical register file be before you start running out of free registers and need to stall fetch? How did changing the reorder buffer and/or scoreboard size and the number of physical registers affect performance? How much did it help to speculate past predicted branches?
The simulator works on Linux machines and on Cygwin. It has been tested on EWS Linux Lab machines in Engineering Hall, and on a machine running RedHat Linux 9.0
Download the tarball for the simulator: ece511-sim.tar.gz
Unzip and untar the simulator by running the command:
This will create a source directory named "ece511". The source directory has the following structure:
+--- ece511 +---- apps +-------- lzw (spec benchmark)
| +-------- gcc (spec benchmark)
| +-------- bzip2 (spec benchmark)
| +-------- parser (spec benchmark)
| +-------- mcf (spec benchmark)
|
+---- sim (the simulator)
Run make in the sim directory:
This compiles the simulator
Compile and run a program on the simulator:
When it gets done the simulator prints out some statistics:
../../sim/pipelined-model mipsver data/smred.in smred.output
loading segment: start 0x00000080, size 0x0000dac4, permissions rwx
Entry point 0x00002214
.text is from 0x00000080 to 0x0000aa40
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 101
active arcs : 323
simplex iterations : 308
flow value : 940002880
new implicit arcs : 1390
active arcs : 1713
simplex iterations : 474
flow value : 550002880
checksum : 2238
optimal
processor halted
Number of cycles run: 62923958
Number of instructions: 9718963
utilization: 0.154456
4x clock gives equivalent speed to single-pump IPC of 0.618
cache hits: 3069555, cache misses: 300202
branches: 2111543, mispredicted 142287
mispredictiction rate: 6.7%
returns: 42498, mispredicted 4560
misprediction rate: 10.7%
accounts for 3.2% of mispredictions
and 2.0% of branches
219.590u 0.170s 3:40.23 99.7% 0+0k 0+0io 399pf+0w
Make changes to the simulator. The simulator code is in the directory ece511/sim. For the third assignment you need only modify the file rename_stage.h. To rebuild the simulator go to the directory ece511/sim and type make.