Instruction Set Architecture
Hennessy,.J. L., Jouppi, N., Baskett, F., Gill, J., "Hardware/Software Tradeoffs for Increased Performance," Proceedings of the Symposium on Architectural Support for Programming, Languages and Operating Systems, pp. 2-11
David A. Patterson, "Reduced instruction set computers", Communications of the ACM, v.28 n.1, p.8-21, Jan. 1985
Colwell, R. P., Hitchcock, C. Y., III, Jensen, E. D., Sprunt, H. M. B. S., and Kollar., C. P., "Computers, Complexity, and Controversy," IEEE Computer Magazine, 18(9):8--19, September 1985.
M. J. Flynn, C. L. Mitchell, and J. M. Mulder, "And Now a Case for More Complex Instruction Sets," IEEE Computer, v.20 n.9, p.71-83, September 1987.
Bhandarkar, D. and Clark, D.W., ``Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization," Proc. Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, April 1991, pp. 310-319.
General Microarchitecture
Ronen, R., Mendelson, A., Lai, K., Lu, S-L., Pollack, F., and Shen, J., "Coming Challenges in Microarchitecture and Architecture," Proceedings of the IEEE, Vol 89, No. 3, March 2001.
Memory Systems
Cuppu, V. and Jacob, B., "Concurrency, Latency, or System Overhead: Which Has the largest Impact on Uniprocessor DRAM-System Performance," Proc. of the 28th International Symposium on Computer Architecture, pp. 62-71, Goteborg, Sweden, June 2001.
Jouppi, N. P., "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. of the 17th International Symposium on Computer Architecture, pp. WRL Technical Note, TN-14, March 1990, Digital Equipment Corporation.
Branch Prediction
J. K. F. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, January 1984.
T-Y Yeh and Y. N. Patt. "Alternative implementation of two-level adaptive branch prediction." In Proceedings of the 19th International Symposium on Computer Architecture, pages 124-134, May 1992.
Wide Fetch
D. H. Friendly, S. J. Patel, and Y. N. Patt, "Alternative fetch and issue techniques from the trace cache fetch mechanism," In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, 1997.
R. F. Krick, G. J. Hinton, M. D. Upton, D. J. Sager, C. W. Lee, "Trace Based Instruction Caching," U.S. Patent #6,018,786, January 25, 2000.
Superscalar Processors
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development Vol. 11, pp. 25-33, January 1967.
Y. N. Patt, W.W. Hwu, and M.C. Shebanow, "HPS, A New Microarchitecture: Rationale and Introduction," Proceedings of the 18th International Microprogramming Workshop, Asilomar, CA Dec. 1985, pp. 103-108.
Smith, J. E., and Sohi, G., "The Microarchitecture of Superscalar Processors," Proceedings of the IEEE, vol. 83, pp 1609--1624, Dec 1995.
Patt, Y. N., Patel, S. J., Evers, M., Friendly, D. H., and Stark, J., "One Billion Transistors, One Uniprocessor, One Chip," IEEE Computer, pages 51--57, Sep. 1997.
Multithreading
Roth, A., and Sohi, G., "Speculative Multithreaded Processors," IEEE Computer, pages 66--72, April 2001.
VLIW
R.P. Colwell, R.P. Nix, J.J. O'Donnell, D.B. Papworth, and P.K. Rodman. "A VLIW architecture for a trace scheduling compiler." In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pages 180-192, April 1987.
B.R. Rau, D.W.L. Yen, W.Yen, and R.A. Towle, The "Cydra 5 departmental supercomputer," IEEE Computer, 22(1):12-35, January 1989.
W. W. Hwu, et al, "Compiler Technology for Future Microprocessors," In IEEE Proceedings, Vol. 83, No. 12, December 1995.
EPIC Architecture
P.P. Chang, N.J. Warter, S.A. Mahlke, W.Y. Chen, and W.W. Hwu. "Three architectural models for compiler-controlled speculative execution." IEEE Transactions on Computers, 44(4):481-494, April 1995.
S. A. Mahlke, W. Y. Chen, R. Bringmann, R. Hank, W. W. Hwu, M. Schlansker and B. Rau, "Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution," In ACM Transactions on Computer Systems, vol. 11, No. 4, November, 1993, pp. 376-408
S. A. Mahlke, R. E. Hank, J. E. MCormick, D. I. August, W. W. Hwu, "A Comparison of Full and Partial Predicated Execution Support for ILP Processors," In Proceedings of the 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June 1995, pp. 138-150.
More to Come...