Question 1.
1. F
The main contribution from von Neumann is the concept
of a stored program that can be modified to change
the behavior of the computer.
2. T
The pipeline registers can potentially increase the latency
of each instruction. Dependencies and hazards can further
increase the latency of each instruction.
3. T
If the throughput fails to increase due to dependencies and
hazards, the performance will not increase.
4. T
This is the basic principle of caching.
Question 2.
1. T
This is the definition of instruction set architecture
2. T
The 32-bit mode has a very different instruction set than the
16-bit mode.
3. T
One size fits all. The size is bound to be too big for some.
4. T
It takes several clock cycles to process
Question 3.
1. F
It works only on the synchronous DRAM.
2. T
3. F
It works with only asynchronous DRAM.
4. T
5. 3
The whole period is 10ns + 60ns + 40ns = 110 ns
Thus, three accesses must overlap to cover the entire latency.
Question 4.
1. T
The desired counting directions for the if branch history patterns are
111 down
110 up
101 up
011 up
The desired counting direction for the loop-back branch history
patterns are:
The desired counting direction for pattern 101 is different
for the two branches.
2. F
The combined global branch pattern is $(11011100) ^ n$.
110 up
101 up
011 up
111 down
110 down
100 up
001 up
011 down
Conflicts for 110 (negative) 011 (negative)
3. T
1101 up
1011 up
0111 down
1110 down
1100 up
1001 up
0011 down
0110 up
There is no conflict
4. T
1101 XOR 0001 = 1100 up
1011 XOR 0100 = 1111 up
0111 XOR 0001 = 0110 down
1110 XOR 0100 = 1010 down
1100 XOR 0001 = 1101 up
1001 XOR 0100 = 1101 up
0011 XOR 0001 = 0010 down
0110 XOR 0100 = 0010 up
There are two conflicts 1101 (positive) and 0010 (negative)
Question 5.
1. F
There are 8 4-byte positions, only 3 of them will
be satisfied with one access.
2. F
If the starting position is at the last 4-byte
position of either bank, the access can not be
satisfied with one access.
3. T
Each fetch can involve at most four banks. There
will be never a situation where a bank will be
needed twice in the same fetch.
4. Possile equivalent solutions:
These assume F to be in terms of words.
1 + Ceiling((F-1)/(L/B)) <= B
Ceiling((F-1)/(B-1)) <= L/B
Ceiling((L/(L-F+1))) <= B
The following assume F to be in terms of bytes:
1 + Ceiling((F-4)/(L/B)) <= B
Ceiling((F-4)/(B-4)) <= L/B
Ceiling((L/(L-F+4))) <= B
Question 6.
1. F
>From Ronen et al., Power = C*V^2*Frequency, where C is the "effective load
capacitance of all devices and wires on the microprocessor". Solve the
equation for C, with P=66.1W, V=1.75V, Freq = 1,800,000,000 and get
C=1.199E-8 . Plug into equation with new V=1.65V, and find the new power to
be 58.76W. (Likewise, could use the ratio of (V2)^2/(V1)^2 ). Therefore,
66.1W-58.76W = 7.34W
2. F
As techology improves, the tradeoffs between instruction set complexity and
architecture/implementation features become LESS constrained.
3. T
All instructions would have their own history table.
4. F
According to the authors, the compiler hints will be necessary.
5. F
See Page 6.
6. T
See pages 8 and 9.
7. T