Each lab has several checkpoints in it. You are required to demo the checkpoints to your TA during each lab session. Many labs build upon past work (if you construct an I2C serial interface in one lab, you will probably need to use it later on), so you are strongly encouraged to understand each assignment. We will upload a solution each week which you are free (and occasionally, encouraged) to use in subsequent weeks.


Lab Assigned Date

Due Date

Primary Reference Documents Additional Reference Documents
Lab 1 1/21/20 1/28/20
Lab 2 1/28/20 2/4/20
Lab 3 2/4/20 2/11/20
Lab 4 2/11/20 2/18/20
Lab 5 2/18/20 2/25/20
Lab 6 2/25/20 3/3/20
Lab 7 3/3/20 3/10/20
  • none
Lab 8 3/10/19 3/31/20
Lab 9    
Lab 10    
Lab 11    
Final Project   5/13 @ 8am Final Demo


Here are some additional resources that will help you with your lab assignments:

Links Document Description
Front Panel API Front Panel online API
Front Panel HDL Front Panel online HDL documentation
Verilog online reference Excellent online reference for Verilog
Python tutorial Online reference for Python