### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 1909853
date_generated | Thu Sep 14 10:10:32 2017 | os_platform | WIN64
product_version | Vivado v2017.2 (64-bit) | project_id | f4183042c61644f58a421d30b2db431a
project_iteration | 2 | random_id | 6685b71d27b15614a8d0011a54dcc10f
registration_id | 211010535_1777502799_210640797_802 | route_design | TRUE
target_device | xc7a75t | target_family | artix7
target_package | fgg484 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Core(TM) i7-5960X CPU @ 3.00GHz | cpu_speed | 3000 MHz
os_name | Microsoft Windows 7 , 64-bit | os_release | Service Pack 1 (build 7601)
system_ram | 137.000 GB | total_processors | 1

vivado_usage

java_command_handlers
addsources=5 | editdelete=1 | newproject=1 | runbitgen=2
runimplementation=1 | runsynthesis=1

other_data
guimode=2

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=13 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=2 | carry4=46 | dna_port=1 | fdce=159
fdpe=47 | fdre=547 | fdse=4 | gnd=9
ibuf=38 | ibufds=1 | lut1=151 | lut2=89
lut3=60 | lut4=201 | lut5=151 | lut6=445
mmcme2_adv=1 | muxf7=8 | obuf=3 | obuft=33
ramb18e1=2 | ramb36e1=1 | ramd32=24 | rams32=8
rams64e=16 | vcc=6
pre_unisim_transformation
bufg=2 | carry4=46 | dna_port=1 | fdce=159
fdpe=47 | fdre=547 | fdse=4 | gnd=9
ibuf=5 | ibufds=1 | iobuf=33 | lut1=151
lut2=89 | lut3=60 | lut4=201 | lut5=101
lut6=395 | lut6_2=50 | mmcme2_adv=1 | obuf=3
ram128x1s=8 | ram32m=4 | ramb18e1=2 | ramb36e1=1
vcc=6

power_opt_design
command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]
usage
bram_ports_augmented=1 | bram_ports_newly_gated=2 | bram_ports_total=6 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=756 | srls_augmented=0
srls_newly_gated=0 | srls_total=0

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-ruledecks=default::[not_specified] | -upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
bufc-1=16 | check-3=2 | reqp-1839=20 | reqp-1840=20
rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-17=1 | timing-18=1 | timing-28=1 | xdch-1=2

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -l=default::[not_specified] | -name=default::[not_specified] | -no_propagation=default::[not_specified]
-return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified] | -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | bram=0.001491 | clocks=0.004098
confidence_level_clock_activity=High | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Low | confidence_level_overall=Low | customer=TBD | customer_class=TBD
devstatic=0.091356 | die=xc7a75tfgg484-1 | dsp_output_toggle=12.500000 | dynamic=0.130427
effective_thetaja=2.7 | enable_probability=0.990000 | family=artix7 | ff_toggle=12.500000
flow_state=routed | heatsink=medium (Medium Profile) | i/o=0.009601 | input_toggle=12.500000
junction_temp=25.6 (C) | logic=0.004625 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000 | mmcm=0.106297 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=0.221783 | output_enable=1.000000 | output_load=5.000000
output_toggle=12.500000 | package=fgg484 | pct_clock_constrained=2.000000 | pct_inputs_defined=2
platform=nt64 | process=typical | ram_enable=50.000000 | ram_write=50.000000
read_saif=False | set/reset_probability=0.000000 | signal_rate=False | signals=0.004316
simulation_file=None | speedgrade=-1 | static_prob=False | temp_grade=commercial
thetajb=6.8 (C/W) | thetasa=4.6 (C/W) | toggle_rate=False | user_board_temp=25.0 (C)
user_effective_thetaja=2.7 | user_junc_temp=25.6 (C) | user_thetajb=6.8 (C/W) | user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000 | vccadc_voltage=1.800000
vccaux_dynamic_current=0.059467 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 | vccaux_static_current=0.018151 | vccaux_total_current=0.077618 | vccaux_voltage=1.800000
vccbram_dynamic_current=0.000133 | vccbram_static_current=0.000294 | vccbram_total_current=0.000428 | vccbram_voltage=1.000000
vccint_dynamic_current=0.016515 | vccint_static_current=0.015190 | vccint_total_current=0.031704 | vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000 | vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000 | vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000 | vcco15_voltage=1.500000
vcco18_dynamic_current=0.003744 | vcco18_static_current=0.004000 | vcco18_total_current=0.007744 | vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000 | vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 | vcco33_static_current=0.000000 | vcco33_total_current=0.000000 | vcco33_voltage=3.300000
version=2017.2

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=2 | bufgctrl_util_percentage=6.25
bufhce_available=96 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=24 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=12 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=24 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=6 | mmcme2_adv_fixed=0 | mmcme2_adv_used=1 | mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=180 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=1 | lvcmos25=0 | lvcmos33=0 | lvds_25=1
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=105 | block_ram_tile_fixed=0 | block_ram_tile_used=2 | block_ram_tile_util_percentage=1.90
ramb18_available=210 | ramb18_fixed=0 | ramb18_used=2 | ramb18_util_percentage=0.95
ramb18e1_only_used=2 | ramb36_fifo_available=105 | ramb36_fifo_fixed=0 | ramb36_fifo_used=1
ramb36_fifo_util_percentage=0.95 | ramb36e1_only_used=1
primitives
bufg_functional_category=Clock | bufg_used=2 | carry4_functional_category=CarryLogic | carry4_used=46
dna_port_functional_category=Others | dna_port_used=1 | fdce_functional_category=Flop & Latch | fdce_used=162
fdpe_functional_category=Flop & Latch | fdpe_used=47 | fdre_functional_category=Flop & Latch | fdre_used=546
fdse_functional_category=Flop & Latch | fdse_used=4 | ibuf_functional_category=IO | ibuf_used=38
lut1_functional_category=LUT | lut1_used=54 | lut2_functional_category=LUT | lut2_used=69
lut3_functional_category=LUT | lut3_used=79 | lut4_functional_category=LUT | lut4_used=133
lut5_functional_category=LUT | lut5_used=166 | lut6_functional_category=LUT | lut6_used=414
mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1 | muxf7_functional_category=MuxFx | muxf7_used=8
obuf_functional_category=IO | obuf_used=3 | obuft_functional_category=IO | obuft_used=33
ramb18e1_functional_category=Block Memory | ramb18e1_used=2 | ramb36e1_functional_category=Block Memory | ramb36e1_used=1
ramd32_functional_category=Distributed Memory | ramd32_used=24 | rams32_functional_category=Distributed Memory | rams32_used=8
rams64e_functional_category=Distributed Memory | rams64e_used=16
slice_logic
f7_muxes_available=31700 | f7_muxes_fixed=0 | f7_muxes_used=8 | f7_muxes_util_percentage=0.03
f8_muxes_available=15850 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=32 | lut_as_logic_available=47200 | lut_as_logic_fixed=0
lut_as_logic_used=788 | lut_as_logic_util_percentage=1.67 | lut_as_memory_available=19000 | lut_as_memory_fixed=0
lut_as_memory_used=32 | lut_as_memory_util_percentage=0.17 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
register_as_flip_flop_available=94400 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=674 | register_as_flip_flop_util_percentage=0.71
register_as_latch_available=94400 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=47200 | slice_luts_fixed=0 | slice_luts_used=820 | slice_luts_util_percentage=1.74
slice_registers_available=94400 | slice_registers_fixed=0 | slice_registers_used=674 | slice_registers_util_percentage=0.71
fully_used_lut_ff_pairs_fixed=0.71 | fully_used_lut_ff_pairs_used=31 | lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=32
lut_as_logic_available=47200 | lut_as_logic_fixed=0 | lut_as_logic_used=788 | lut_as_logic_util_percentage=1.67
lut_as_memory_available=19000 | lut_as_memory_fixed=0 | lut_as_memory_used=32 | lut_as_memory_util_percentage=0.17
lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0 | lut_ff_pairs_with_one_unused_flip_flop_fixed=0 | lut_ff_pairs_with_one_unused_flip_flop_used=278
lut_ff_pairs_with_one_unused_lut_output_fixed=278 | lut_ff_pairs_with_one_unused_lut_output_used=269 | lut_flip_flop_pairs_available=47200 | lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=333 | lut_flip_flop_pairs_util_percentage=0.71 | slice_available=15850 | slice_fixed=0
slice_used=296 | slice_util_percentage=1.87 | slicel_fixed=0 | slicel_used=189
slicem_fixed=0 | slicem_used=107 | unique_control_sets_used=51 | using_o5_and_o6_fixed=51
using_o5_and_o6_used=16 | using_o5_output_only_fixed=16 | using_o5_output_only_used=0 | using_o6_output_only_fixed=0
using_o6_output_only_used=16
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=1 | dna_port_util_percentage=100.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

router
usage
actual_expansions=906412 | bogomips=0 | bram18=2 | bram36=1
bufg=0 | bufr=0 | congestion_level=0 | ctrls=51
dsp=0 | effort=2 | estimated_expansions=970020 | ff=759
global_clocks=2 | high_fanout_nets=2 | iob=41 | lut=886
movable_instances=1876 | nets=2359 | pins=11178 | pll=0
router_runtime=0.000000 | router_timing_driven=1 | threads=2 | timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a75tfgg484-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=Framework | -verilog_define=default::[not_specified]
usage
elapsed=00:00:50s | hls_ip=0 | memory_gain=456.496MB | memory_peak=687.227MB