Date |
Topic |
Reading |
08/27/2019 | Introduction | Weste & Harris: 1.1, 1.5.1, 1.6 |
08/29/2019 | IC Fabrication | Weste & Harris: 1.3, 1.5.1-2 |
09/03/2019 | Circuits and Layout, Circuits and Layout-full equations | Weste & Harris: 1.4, 1.5.3-5 |
09/05/2019 | MIPS Case Study | Weste & Harris: 1.7-1.12 |
09/10/2019 | CMOS Transistor Theory , CMOS Transistor Theory -full equations | Weste & Harris: 2.1-2.4 |
09/12/2019 | DC and Transient Response, DC and Transient Response-full equations | Weste & Harris: 2.5, 4.1-4.3 |
09/13/2019 | (MP0 Report Due) | |
09/17/2019 | SPICE, MP1 Introduction | Weste & Harris: 8.1, 8.2 |
09/19/2019 | Combinational Circuit Design , Combinational Circuit Design-full equations (HW1 Due) | Weste & Harris: 4.4.1-4.4.4; 4.5.1; 9.1-9.2.2 |
09/24/2019 | Sequential Circuit Design , Sequential Circuit Design-full equations | Weste & Harris: 10.1-10.3.4 |
09/26/2019 | Wires , Wires-full equations | Weste & Harris: 6.1-6.2.2; 6.3.1-6.3.3; 6.4.1-6.4.2 |
10/01/2019 | Adders, Adders-full equations | Weste & Harris: 11.1-11.2.2.8 |
10/03/2019 | Multipliers and Other FUs, Multipliers and Other FUs-full equations | Weste & Harris: 11.3-4; 11.8-9 |
10/04/2019 | (MP1 Report Due) | |
10/08/2019 | SRAMs, MP2 Introduction | Weste & Harris: 12.1-12.2.5 and 12.5 |
10/10/2019 | CAMs, ROMs, PLAs, CAMs, ROMs, PLAs-full equations | Weste & Harris: 12.4-12.7 |
10/15/2019 | Modeling Digital Systems, Verilog (HW2 Due) | Weste & Harris: Appendix A |
10/17/2019 | Midterm Overview | |
10/22/2019 | Midterm | |
10/24/2019 | Circuit Pitfalls and Design for Test , Circuit Pitfalls and Design for Test-full equations | Weste & Harris: 7.1-7.3; 15.1-15.7 |
10/29/2019 | Design for Low Power , Design for Low Power-full equations | Weste & Harris: 5.1-5.3 |
10/31/2019 | Special topics: Packaging, power and clock | Weste & Harris: 13.1-13.4 |
11/05/2019 | VLSI Design Styles | Weste & Harris: 14.3 |
11/01/2019 | (MP2 Checkpoint Report Due) | |
11/07/2019 | VLSI CAD Tools | Weste & Harris: 14.4 |
11/12/2019 |
G. De Micheli: chapters 4 & 5 Optional: |
|
11/14/2019 | Logic Synthesis |
G. De Micheli: 2.5-2.5.1 |
11/19/2019 | Logic Synthesis |
G. De Micheli: 2.5.2 |
11/21/2019 | Partitioning and Floorplan, MP3 Introduction | N. Sherwani: 5.1-5.4, 6.1 |
11/22/2019 | (MP2 Report Due) | |
11/26/2017 | (Thanksgiving Break) | |
11/28/2017 | (Thanksgiving Break) | |
12/03/2019 | Placement and Routing (HW3 Due) | N. Sherwani: 7-7.1, 7.4, 8-8.4, 9.1.3, 9.4.2 |
12/05/2019 | Final Exam Overview | |
12/10/2019 | Final Exam | |
12/13/2019 | (MP3 Report Due, Hard Deadline) |