ECE 110/120 Honors Lab Section : DES Encryption on FPGA

Statement of Purpose

Write an implementation of the Data Encryption Standard (DES) in (a) a HDL, and (b) a high-level langauage, and run it on an FPGA for benchmarking. Will probably use the ECB mode of operation — security isn't a concern for DES in any case. Considering using PYNQ FPGA's that come with both a microprocessor and logic units that will allow benchmarking on a single device – possibly encryption in software and decryption in hardware, or vice versa.

Background Research

Implementing DES in hardware isn't new — in fact, DES was designed to use operations that are efficient at the bit level to aid hardware implementations. My interest in this project comes from the benchmarking — by how much does software slow you down, and how to quantify the reduction in speed from special purpose hardware. AES (DES' successor), is generally implemented in hardware as well: x86 has assembly instructions for AES, the most common of which is AESENC.

Block Diagram / Flow Chart

System Overview

Input plaintext and key from PC. Encrypt using software, then pass ciphertext and key to hardware. Decrypt using hardware, then return plaintext to PC. Diff the input and output to check corruption of data. Run in a loop to benchmark, using the microprocessor to send a signal when encryption step is completed.

Parts

This is the same board used by ECE527: https://courses.engr.illinois.edu/ece527/fa2021/mach_probs.html: in case the department has extra boards, there's no need to order another.

Possible Challenges

Making a robust HDL implementation of DES.

References

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=886736