Tue 6:00 P.M. - 7 P.M.
Meet Our Team
Mingyuan Han, mh24, ECE120
Ziyan Chen, ziyanc3, ECE120
Project Proposal
1.0 Introduction
1.1 Purpose Statement
Arithmetic Logic Unit (ALU) is the foundation building block operating on integer binary numbers that constructs our Central Processing Unit (CPU), Graphics Processing Unit (GPU), and Floating-Point Unit (FPU), etc. We are building the ALU to better understand the functioning of our computers and to incorporate our knowledge of bitwise logic and logic gates. By constructing the arithmetic logic units, we will be able to use hardware description language to program our units and observe the signal behavior while processing.
1.2 Background Research
Our motivation begins with our obsession towards those tiny and micro construction of our circuits. We are interested in microchips that drives our life everywhere in the world. We hope to understand from the foundation of those computation and signal processing. We went through several projects like face recognition using Eigen Values, logic analyzer, and homebrew CPU. After comparison on those projects, we feel strongly attracted by these logic circuits that build up our central processing unit.
2.0 Design
The above is the flowchart of addition and subtraction operation of ALU. First, we want to take in three inputs, A, B and C. Depending on the value of input C, the ALU will decide to carry out addition or abstraction. If the result’s return is false, then the input B will be inverted and add 1. After that, the ALU will add two numbers together to get the final result. If the result’s return is 1, the ALU will directly add two numbers together. One the ALU gets the result, it will check whether or not the result overflows. If the result overflows, it will output error, otherwise it will output the result.
This is the flowchart of multiplication. The ALU will first judge whether the bit of multiplier is 1 or not. If the multiplier is equals to 1, the ALU will add the multiplicand to product and place the result in product register. If the bit is equal to 0, there is no instruction. After that, the ALU will shift the multiplicand register left 1 bit and shift the multiplier register right 1 bit. Then, it will check the number of repetition. If the number repetition is smaller than needed, the ALU will go back to the beginning and check whether the multiplier is equals to 0. If number of repetition is met, the ALU will output the result.
This is the flowchart of division. The ALU will first subtract the divisor register from the remainder register and place the result in the remainder register. After that, the ALU will test whether the remainder is bigger than 0. If the remainder is bigger than 0, the ALU will shift the quotient register to the left and set the new rightmost bit to 1. If the remainder is smaller than 0, the ALU will restore the original value by adding the divisor register to the remainder register and placing the sum in the remainder register. Also, the ALU will shift the quotient register to the left and set the least significant bit to 0. After that, the ALU will shift the divisor register to the right for 1 bit. Then, it will check the number of repetition. If the number repetition is smaller than needed, the ALU will go back to the beginning and carries this loop again. If the number of repetition is net, the ALU will output the result.
3.0 Components
- SN74AHCT86N (XOR Gate)
- SN74LS04N (NOT Gate)
- SN7432N (OR GATE)
- SN74LS08N (AND Gate)
- DIP Switch - 1825057-7
- Breadboard 6.5inch * 2.2inch
- LEDs
4.0 Challenges
- Binary Multiplication & Division
- Hardware Programming using VHDL
5.0 Reference
[1]R. Mitchell, "How to Build Your Own Discrete 4-Bit ALU", Allaboutcircuits.com, 2016. [Online]. Available: https://www.allaboutcircuits.com/projects/how-to-build-your-own-discrete-4-bit-alu/. [Accessed: 27- Jan- 2019].
[2]"Lecture 8: Binary Multiplication & Division."
[3]"Lecture5 Multiplication and Division."
[4]B. Easter, ALU Design. youtube, 2016.
Project Final Report
Attachments:
MULTIPLICATION FLOW CHART.png (image/png)
MULTIPLICATION FLOW CHART.png (image/png)
DIVISION FLOW CHART.png (image/png)
Final_Project_Lab_Report_ALU_Team.pdf (application/pdf)
Comments:
Your project seems a lot interesting to implement, however a lot of students in the past have already tried to build something similar, ALU, RAM Cell, Clock cycle etc., so i would say look for the past projects and try to get some insight from them. Also, you can have a look at Ben Eater's website as he has also tried to implement something similar (https://eater.net/8bit)
Posted by dv5 at Feb 12, 2019 18:41
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2 week check in completed
Posted by chorn4 at Apr 09, 2019 18:29
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Demoed! Good job this semester!
Posted by chorn4 at Apr 30, 2019 13:57
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