1) Modeling process variation and wear-out (2 lectures):

1a) VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008.

1b) Facelift: Hiding and Slowing Down Aging in Multicores by Abhishek Tiwari and Josep Torrellas, 41st International Symposium on Microarchitecture (MICRO), November 2008.

2) Tolerating/mitigating variation with body biasing (1 lecture):

2a) Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, 40th International Symposium on Microarchitecture (MICRO), December 2007.

3) Tolerating/mitigating variation with timing speculation (2 lectures):

3a) D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Zeisler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. Razor: A lowpower pipeline based on circuit-level timing speculation. In International Symposium on Microarchitecture, December 2003.

3b) BlueShift: Designing Processors for Timing Speculation from the Ground Up by Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles, 15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009.

4) Tolerating/mitigating variation with application scheduling (1 lecture):

4a) Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors by Radu Teodorescu and Josep Torrellas, 35th Annual International Symposium on Computer Architecture (ISCA), June 2008.

5) Reducing voltage guardbands (3 lectures):

5a) Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge Near-Threshold Computing: Reclaiming Moores Law Through Energy Efficient Integrated Circuits, Proceedings of the IEEE, February 2010.

5b) C. R. Lefurgy, A. J. Drake, M. S. Floyd, M. S. Allen-Ware, B. Brock, J. A. Tierno, and J. B. Carter. Active management of timing guardband to save energy in POWER7. In International Symposium on Microarchitecture (MICRO), pages 1{11, December 2011.

5c) Anys Bacha and Radu Teodorescu, Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors, International Symposium on Computer Architecture (ISCA), June 2013.

6) Managing voltage droops (1 lecture):

6a) Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks. Voltage Smoothing: Characterizing and Mitigating Voltage Noise in a Production Processor Using Software-Guided Thread Scheduling, 43rd Annual International Symposium on Microarchitecture (Micro-43), Atlanta, GA, Dec. 2010.

7) Design for low voltage (2 lectures):

7a) ScalCore: Designing a Core for Voltage Scalability by Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, and Asit Mishra, International Symposium on High Performance Computer Architecture (HPCA), March 2016.

7b) Tangle: Route-Oriented Dynamic Voltage Minimization for Variation-Afflicted, Energy-Efficient On-Chip Networks by Amin Ansari, Asit Mishra, Jianping Xu, and Josep Torrellas, International Symposium on High Performance Computer Architecture (HPCA), February 2014.

8) Efficient DRAM/eDRAM design (3 lectures):

8a) C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S.-L. Lu. Reducing cache power with low-cost, multi-bit error-correcting codes. In International Symposium on Computer Architecture (ISCA), 2010.

8b) Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules by Aditya Agrawal, Amin Ansari, and Josep Torrellas, International Symposium on High Performance Computer Architecture (HPCA), February 2014.

8c) J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu, An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms, in ISCA, Jun. 2013.

9) Power gating and microcheckpointing (1 lecture):

9a) Xiang Pan and Radu Teodorescu, NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores, IEEE International Conference on Computer Design (ICCD), October 2014.

10) On-chip controllers (3 lectures):

10a) Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures by Raghavendra Pothukuchi, Amin Ansari, Petros Voulgaris, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2016.

10b) Augusto Vega, Alper Buyuktosunoglu, Heather Hanson, Pradip Bose, Srinivasan Ramani. Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control, in MICRO, 2013.

10c) Opeoluwa Matthews, Meng Zhang, and Daniel J. Sorin. "Scalably Verifiable Dynamic Power Management." 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014.

11) Distributing the heat (1 lecture):

11a) Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system Michael Powell, Mohamed Gomaa, and T. N. Vijaykumar In Proceedings of the 11th International Conference on architectural support for programming languages and operating systems (ASPLOS), pages 260-270, October 2004.

12) 3D stacked architectures (4 lectures):

12a) B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. Loh, D. McCauley, P. Morrow, D. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb, Die Stacking (3D) Microarchitecture, in IEEE International Symposium on Microarchitecture, Dec. 2006.

12b) G. Loh, 3D-Stacked Memory Architectures for Multi-core Processors, in International Symposium on Computer Architecture, Jun. 2008.

12c) Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Trevor Mudge, David Blaauw, and Dennis Sylvester IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013.

12d) P. Emma, A. Buyuktosunoglu, M. Healy, K. Kailas, V. Puente, R. Yu, A. Hartstein, P. Bose, and J. Moreno., 3D Stacking of High- Performance Processors, in IEEE International Symposium on High- Performance Computer Architecture, Feb. 2014.

13) System architectures: extreme scale architectures (2 lectures):

13a) Extreme-Scale Computer Architecture: Energy Efficiency from the Ground Up by Josep Torrellas, International Conference on Design, Automation and Test in Europe (DATE), March 2014.

13b) Runnemede: An Architecture for Ubiquitous High-Performance Computing by Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua Fryman, Ivan Ganev, Roger A. Golliver, Rob Knauerhase, Richard Lethin, Benoit Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, and Jianping Xu, International Symposium on High Performance Computer Architecture (HPCA), February 2013.

14) System architectures: Mobile systems (1 lecture):

14a) M. Halpern, Y. Zhu, and V. J. Reddi, Mobile CPUs rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction, in 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), March 2016.