Title: Package/Board level signal integrity analysis using Neural Networks
Abstract: With the growing need for semiconductor products, it has become crucial to find efficient methods to design, analyze and validate these products. As the interface speed increases, the analysis and simulation of these systems are becoming challenging and time consuming. During the design process, any approximations/assumptions made can lead to errors and be time consuming. This presentation discusses the development of a fast learned model to replace the conventional slow model in design and optimization. While the design process can be challenging, after the design process, accurate analysis of these networks is necessary. These analyses are often performed in time domain using a time-consuming approach of the time marching methods. Analyzing systems in time domain without order reduction results in extreme inefficiency and inaccuracy. Therefore, in this presentation, an efficient and reliable method of reducing the order of system (from complex high-order model to simple low order model) for subsequent time domain simulation will also be discussed.