Lectures

Date

Slides

Accompanying Material

Recordings

• Chapter 38, Design Automation for Microelectronics, Handbook of Automation
• Tutorial: System-on-Chip Design

• Verilog Overview
• The Verilog Hardware Description Language 5th Edition

• Collaborative Computing for Heterogeneous Integrated Systems

• Improving Embedded Software Design and Integration in SOCs

• A Novel SoC Architecture on FPGA for Ultra Fast Face Detection

• Codex-dp: Co-Design of Communicating Systems Using Dynamic Programming 
• Parallel Code-Specific CPU Simulation with Dynamic Phase Convergence Modeling for HW/SW Co-Design
• A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration
• Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

• Designing High-Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis
• Improving polyhedral code generation for high-level synthesis
• Improving high-level synthesis optimization opportunity through polyhedral transformations

• Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s  

• Material on ILP from "Synthesis and optimization for digital circuits"

• Low-Power High-Level Synthesis for FPGA Architectures

• In-Datacenter Performance Analysis of a Tensor Processing Unit

• Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
• In-Datacenter Performance Analysis of a Tensor Processing Unit

• Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
• High-Performance Video Content Recognition with Long-term Recurrent Convolutional Network for FPGA
• DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs

• Research Infrastructures for Hardware Accelerators
• DEEP-SUBMICRON MICROPROCESSOR DESIGN ISSUES

• EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
• SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems

• FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs
• Multilevel Granularity Parallelism Synthesis on FPGAs  

• FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache

• LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems
• Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis 
• From Software Threads to Parallel Hardware in High-Level Synthesis for FPGAs