Instructor

Deming Chen (dchen AT illinois.edu)

Office hours: Tuesday 4:00 - 5:00 PM Central Time, online. Same Zoom link as the lecture one. 

http://www.ece.illinois.edu/directory/profile.asp?dchen

Teaching Assistant

-Mang Yu (mangyu2 AT illinois.edu)

Office hours: Monday 1:00 - 2:00 PM CST, online. Same Zoom link as the lecture one.

-Paul Jeong (hyunmin2 AT illinois.edu)

Office hours: Monday 2:00 – 3:00 PM CST, online. Same Zoom link as the lecture one.

Credits

4 hours

Lectures

 Online Zoom Meeting

Time: Tuesday/Thursday 11:00 - 12:20 PM Central Time

https://illinois.zoom.us/j/98759061081?pwd=ZE9UbmxBNk5Za2FTNmlLQThDZWg1QT09

Zoom Meeting ID: 987 5906 1081

Passcode: 077252

Lab

4022 ECE Building (only for tasks where in-person contact is necessary)

Prerequisites

ECE 425 (or equivalent), ECE 391 (or equivalent)

Piazza Homepage

Link: https://piazza.com/illinois/fall2020/ece527

General Description

System-on-a-chip

(SOC) is an idea of integrating all components of a computer system into a single chip. SOC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. Gartner regards them as the most important type of semiconductor device since the development of the microprocessor. An important enabler for the design of SOCs is the availability of semiconductor intellectual property (IP), which allows a SOC designer to include predefined circuitries, cutting development cycle while increasing product functionality, performance and quality. The implementation of these systems of both hardware and software components and the interaction between hardware and software is an essential part of the design. This course will cover SOC topics on design process, modeling and analysis, design methodology and platform, hardware/software co-design, behavioral synthesis, embedded software, verification, and design space exploration. With a focus on learning of the current SOC design and research topics, students are given opportunities to carry out class projects based on their own interest. Class projects can include software/hardware partitioning, hardware implementation of video compression algorithms, and synthesis for application specific instruction set processors (ASIP). Platform FPGA boards and digital cameras are provided to students to prototype, test, and evaluate their SOC designs.

Textbooks

• Class Notes

Supplementary Materials

• G. De Micheli, R. Ernst, and W. Wolf, eds., Readings in Hardware/Software Co-Design, Morgan Kaufmann, 2001.
• De Micheli; Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994.
• A. Jerraya and W. Wolf, eds., Multiprocessor Systems-on-Chips, Morgan Kaufmann, 2004.
• Grant Martin and Henry Chang, Winning the SoC Revolution: Experiences in Real Design, Kluwer, 2003.
• Related Research Papers.

Grading Policy

Machine problem 1: 5% (70% actual work + 30% report)

Machine problem 2: 8% (70% actual work + 30% report)

Machine problem 3: 5% (70% actual work + 30% report)

Machine problem 4: 10% (70% actual work + 30% report)

 

Class participation: 2%

Homework: 10%

Midterm: 20%

Research Project 40%: (70% actual work + 20% report + 10% presentation)

Lateness Policy

15% off/day, cannot be more than 3 days late.