Welcome to ECE 511! Course Info and Syllabus


Course Info: Lectures will be online on Zoom (TR 2:00-3:20 PM CST).
Recordings will be on Zoom Cloud, see Lectures page.
Please join Campuswire (join code: 6285) for Q&A.
Assignments should be submitted on Compass.
Course Description: Advanced concepts in computer architecture: design, management, and modeling of memory hierarchies; pipelined computers; and multiple processor systems. Emphasis on hardware alternatives in detail and their relation to system performance and cost. More specifically, assuming knowledge of pipelined processors with cache memories, as studied in depth in ECE 411, we continue with advanced techniques for extracting greater levels of instruction-level parallelism and memory-level parallelism in ECE 511. The former exploits opportunities for parallel execution of instructions from an inherently serial instruction stream, while the latter attempts to overlap increasing memory access latency with other useful work. We will study the memory hierarchy as well as virtual memory, and will also cover processor chips that with multiple cores, where concurrency is extracted from multiple sequential threads of execution.


Course Prerequisites:

• ECE 411 or CS433.

• C/C++ programming.

• SystemVerilog.