Course Websites

ECE 498 SJP - Accelerator Architectures

Last offered Spring 2023

Official Description

Subject offerings of new and developing areas of knowledge in electrical and computer engineering intended to augment the existing curriculum. See Class Schedule or departmental course information for topics and prerequisites. Course Information: 0 to 4 undergraduate hours. 0 to 4 graduate hours. May be repeated in the same or separate terms if topics vary.

Section Description

Specialized, accelerator chip architectures are an important category of computing devices due to the significant performance/power/area advantage they bring over general purpose architectures. Accelerator architectures are optimized for performance, power, energy or cost for the needs of a specific class of applications, specialized for their computational needs. Examples include graphics processing unit (GPU) architectures, ML accelerators, digital signal processors, and mobile processors. This course will explore various design principles for families of accelerator architectures, examining implications on computing and dataflow, parallelism, memory hierarchies, interconnects, and software. There will be a team-oriented design project in which teams build their own accelerator architecture in a design language such as System Verilog following an ASIC-like flow for an open RISC-V core for a class of workloads of their choosing. Prerequisites: ECE 411 or CS 433, experience with System

Related Faculty

TitleSectionCRNTypeHoursTimesDaysLocationInstructor
Accelerator ArchitecturesSJP48559PKG4 -    Sanjay Patel
Accelerator ArchitecturesSJP48559PKG41230 - 1350 T R  3015 Electrical & Computer Eng Bldg Sanjay Patel