ECE 498NSU/NSG: Resource-efficient Machine Learning for the Edge

Description: This course will present challenges in implementing machine learning algorithms on resource-constrained hardware platforms at the Edge such as wearables, IoTs, autonomous vehicles, and biomedical devices. Single-stage classifiers will be discussed first followed by deep neural networks. Finite-precision analysis will be employed to design fixed-point networks to minimize energy, latency, and memory footprint. Training algorithms of both single-stage and deep nets (back-prop) will be presented followed by training in fixed-point. Algorithm-to-architecture mapping techniques will be explored to trade-off energy-latency-accuracy in deep learning digital accelerators and analog in-memory architectures. Fundamentals of learning behavior, fixed-point analysis, architectural energy, and delay models will be introduced just-in-time throughout the course. Case studies of hardware (architecture and circuit) realizations of deep learning systems will also be presented. Homeworks will include a mix of analysis and programming exercises in Python and Verilog leading up to a term project involving the implementation of deep nets on an embedded hardware platform such as an FPGA/MCU. Graduate students additionally will submit a term paper based on the literature review of a specific topic of their interest.

Syllabus: ECE 498NSU/NSG syllabus

Prerequisite: ECE 385 and ECE 313 or equivalent. Students should be familiar with programming in Python. HDL (Verilog) programming experience is desirable.

Time and Place: 11:00am-12:20pm, TuTh, ECEB 2013

Professor Naresh Shanbhag

Department of Electrical and Computer Engineering

Web page: http://shanbhag.ece.illinois.edu

Office Hours: Thursdays at 2:00pm-3:00pm in CSL 414

Email: shanbhag AT illinois DOT edu