ECE 498NSU/598NSG: Deep Learning in Hardware

Description: This course will present challenges in implementing deep learning algorithms on resource-constrained hardware platforms at the Edge such as wearables, IoTs, autonomous vehicles, and biomedical devices. Fixed-point requirements of deep for deep neural networks and convolutional neural networks including the back-prop based training will be studied. Algorithm-to-architecture mapping techniques will be explored to trade-off energy-latency-accuracy in deep learning digital accelerators and analog in-memory architectures. Fundamentals of learning behavior, fixed-point analysis, architectural energy and delay models will be introduced in just-in-time manner throughout the course. Case studies of hardware (architecture and circuit) realizations of deep learning systems will be presented. Homeworks will include a mix of analysis and programming exercises in Python and Verilog leading up to a term project.

Syllabus: ECE 498NSU/598NSG syllabus

Prerequisite: ECE 385 and ECE 313 or equivalent. Students should be familiar with programming in Python. HDL (Verilog) programming experience is desirable.

Time and Place: 11:00am-12:20pm, TuTh ONL

Professor Naresh Shanbhag

Department of Electrical and Computer Engineering

Web page: http://shanbhag.ece.illinois.edu

Office/Recitation Hours: 2:00pm-3:00pm Tu ONL

Email: shanbhag AT illinois DOT edu