Some thoughts on this document

• We want this document to be living.

  • We should have the source checked in somewhere (probably in a repo next to gem5).
  • We should force people to make updates when they break things.
  • We should have the source for the examples checked into the gem5 repo, and have tests that run them.

• It may be a good idea to add example exercises at the end of each chapter. These could be things that are good for a classroom or just good things to try out.

• Adding a more “realistic” example in Part I would make the book a little more interesting. Giving readers an idea of what’s possible early would set the stage better.

An outline:

1. Part I: Getting started

   Done-ish

2. Developing with gem5

   1. Creating a new SimObject

   2. Debugging support in gem5

   3. Simple event-driven model

   4. Adding parameters to SimObjects

   5. Creating a new MemObject with master/slave ports

   6. A more complex SimObject: Simple Uniprocessor cache

   7. A simple CPU model (Code mostly done, but prose not written)

   8. Contributing back to gem5 (not done)

      1. Style guidelines
      2. Mercurial queues
      3. Reviewboard

   9. Running tests (not done)

3. Using Ruby cache coherence model

   1. Overview of Ruby
   2. Ruby’s cache coherence protocols
   3. Understanding the protocol trace
   4. Ruby’s network topologies
   5. Writing a new protocol
   6. Debugging a protocol
   7. Extending the SLICC language

4. Full system simulation

   1. Introduction
   2. Simple FS config file
   3. Building a kernel for gem5 (on my website, but not here)
   4. Building a disk image for gem5 (ditto)
   5. ARM simulation (to do)
   6. More on X86 simulation (to do)

5. Advanced gem5 usage (to do)

   1. Checkpoint creation and restoring
   2. ISA language
   3. Using m5ops
   4. Using traces

6. An overview of common SimObjects (to do)

   1. CPUs

      1. CPU models
      2. Dynamically switching CPUs

   2. Classic memory system

      1. Random note: All controllers that issue coherent requests are required to have a cache attached to them. For instance, you have to have a cache on the IOBus or else there are weird errors.

   3. System

7. External projects and gem5

   1. Power models
   2. GPU models
   3. External simulation infrastructure

Todo

Add information about address ranges and interleaved address ranges.

Todo list

Todo

Finish the previous paragraph about how it is a good idea to understand what your tools are actually doing.

(The original entry is located in learning_gem5/intro.rst, line 22.)

Todo

should add a list of terms. Things like “simulated system” vs “host system”, etc.

(The original entry is located in learning_gem5/intro.rst, line 26.)

Todo

Add a pointer to the gem5 docker image. In fact, we may want to have a docker image for each section.

(The original entry is located in learning_gem5/part1/building.rst, line 12.)

Todo

We should add links to SimObjects like Cache that point to the doxygen on gem5’s site.

(The original entry is located in learning_gem5/part1/cache_config.rst, line 31.)

Todo

Explain what event-driven programming is

(The original entry is located in learning_gem5/part2/events.rst, line 14.)

Todo

make a section on the SConscript build system which discuss all of the functions.

(The original entry is located in learning_gem5/part2/helloobject.rst, line 178.)

Todo

Explain params etc. Overall, the tag store is not a great example for this, but we’ll leave it for now.

(The original entry is located in learning_gem5/part2/simobject-old.rst, line 99.)

Todo

Talk about other kind of proxy parameters somewhere.

(The original entry is located in learning_gem5/part2/simplecache.rst, line 49.)

Todo

Talk about how state machine files are SimObjects and how they inherit from AbstractController

(The original entry is located in learning_gem5/part3/MSI/cache-intro.rst, line 75.)

Todo

Add more details about the random tester.

(The original entry is located in learning_gem5/part3/MSI/debugging.rst, line 44.)

Todo

Add a chapter on default protocols in gem5

(The original entry is located in learning_gem5/part3/index.rst, line 24.)

Todo

Make the MSI one chapter

(The original entry is located in learning_gem5/part3/index.rst, line 28.)

Todo

Talk about when to use Ruby and when to use classic caches

(The original entry is located in learning_gem5/part3/intro.rst, line 37.)

Todo

Put in picture of Ruby

(The original entry is located in learning_gem5/part3/intro.rst, line 41.)

Todo

Talk about message buffers

(The original entry is located in learning_gem5/part3/intro.rst, line 45.)

Todo

Talk about the network

(The original entry is located in learning_gem5/part3/intro.rst, line 49.)

Todo

Make sure there is a link to the gem5 source here

(The original entry is located in learning_gem5/part5/fs_config.rst, line 24.)

Todo

Update all SimObjects to point to the gem5 source code.

(The original entry is located in learning_gem5/part5/fs_config.rst, line 40.)

Todo

This bad addr thing could be made more clear.

(The original entry is located in learning_gem5/part5/fs_config.rst, line 89.)

Todo

Other differences between SE and FS mode...

(The original entry is located in learning_gem5/part5/intro.rst, line 33.)

Todo

Add information about address ranges and interleaved address ranges.

(The original entry is located in learning_gem5/thoughts.rst, line 64.)